A cache is a relatively high-speed, small, local memory which is used to provide a local storage (a buffer store) for frequently accessed memory locations of a larger, relatively slow, main memory ( a backing store). By storing the information or a copy of the information locally, the cache is able to intercept memory references and handle them directly without transferring the request to the main memory over a system bus. The result is lower traffic on the memory bus and decreased latency on the CPU bus to the requesting processor.
The above-referenced U.S. Pat. No. 5,210,845 discloses a cache controller having a tag random access memory (RAM) which is configured into two ways. Each way includes tag and valid-bit storage for associatively searching the directory for cache data-array addresses. The external cache memory is organized such that both ways are simultaneously available to a number of available memory modules in the system to thereby allow the way access time to occur in parallel with the tag lookup.
The above-referenced U.S. Pat. No. 5,339,399 discloses a method and means for managing complex timing cycles in the cache controller of U.S. Pat. No. 5,210,845. Output enable activation time is very critical to synchronizing the external cache with an Intel 80486.TM. microprocessor operating at 33MHz. As soon as a cycle starts by presenting an address to the tag RAM, the time that the tag RAM needs in order to signal that the address is a hit or a miss is almost half into the next clock period. To manage this timing the U.S. Pat. No. 5,339,399 provides control logic that comprises a first address latch, a second address latch and a clocking means. The clocking means includes a first clock signal for capturing a current address on an input address bus into one of said first and second address latches at the beginning of a current cycle. The clocking means further includes a second clock signal for capturing a next address on the input address bus into the other one of said first and second address latches at the beginning of a next cycle, the other of said latches holding the current address until said current cycle ends. Means are provided for alternately selecting one of said first and second latches on successive cycles of said clocking means to receive an input address at the successive clock cycles. A multiplexer (MUX) controls which of said current address and said next address is gated to said tag RAM. A snoop cycle signal line is provided for signalling that a snoop address is on the address bus. A first snoop latch connected to the address bus and responsive to the snoop cycle signal line stores the snoop address. A second snoop latch connected to the first snoop latch address bus and responsive to a snoop cycle signal line is provided to further buffer the snoop address. A third clock signal is provided for capturing the contents of the first snoop latch into the second snoop latch to thereby extend the time that the snoop address is available at the input to the tag RAM. The MUX further includes means for controlling which of the current address and the next address and the snoop address is gated to the tag RAM.
Tracking the internal cycle of the cache controller described in the above-referenced applications could be a complicated task with many terms contributing to the equations. This would slow down the operation to such a degree that the cache controller would not be commercially practicable.
It is therefore an object of the present invention to provide a means for tracking processor cycles in a controller for a data cache that reduces the terms involved to thereby speed up the operation.